The present invention relates generally to semiconductor components, and more particularly to the formation of integrated circuit capacitors, and even more particularly to the formation of high capacitance value integrated circuit capacitors.
In the past, standard methods employed to integrate capacitive structures within integrated circuits included a sandwich of silicon, thin-oxide, and polysilicon. It is known in the art that the value of capacitance per unit area increases with thinner dielectric film or with higher dielectric constant material. Therefore, nanometer thin silicon oxide, silicon nitride, oxi-nitride or ferroelectric dielectric material is typically deployed to form capacitors. Dielectric oxides formed with silicon have low dielectric constants of 3.9. The resultant capacitors are limited to pico-Farad or smaller values due to the low value dielectric constant creating a low value capacitance per unit area and correspondingly limited due to size restrictions, i.e., “silicon real estate”, for the total area of the integrated circuit layout configuration.
Efforts to increase capacitance by further thinning the dielectric layer are constrained due voltage breakdown characteristics of the dielectric layer. Enlarging the area of a capacitor to increase the total capacitance often creates reliability issues due to photomask defect density characteristics creating pinholes in the dielectric layers of the capacitors. Therefore, realistic expectations for maximum capacitance values using present art technology are in the range of five to ten pico-Farads. The total number of capacitors per integrated circuit die is also limited by the physical size of the capacitors.
Typically, larger value capacitors required for circuits are incorporated externally, to the integrated circuit, as discrete capacitors.
Efforts to increase integrated circuit “real estate” efficiency have been investigated, including the formation of capacitors between metal lines or between layers of interconnect metal. However, these methods are not easily implemented due to the effects of parasitic capacitances between interconnect metals. Therefore, formation of integrated capacitors within integrated circuits is generally incorporated between the semiconducting surface and the first metal lines.
Furthermore, thick inter-layer dielectric and low-k dielectric films are intentionally employed to reduce unwanted parasitic capacitances between interconnect metal layers and between metal lines having narrow spacing within same metal layer. The resultant effect negatively impacts the maximum capacitance per unit area that can be achieved.
Additional methods for increasing the relative per unit area capacitance include the creation of vertically integrated capacitor structures. However, the resulting wafer process is more complex and more costly than standard processed wafers with laterally integrated components.
Therefore, what is needed is a cost effective method of providing larger per unit capacitance values, i.e., in the nano-range, incorporated in a standard integrated circuit wafer process.